This application is related to Japanese Patent Application No. 2000-133751 filed on May 2, 2000, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to an integrated CMOS semiconductor circuit. More particularly it relates to an integrated CMOS semiconductor circuit applicable for low power consumption-type, battery-operated portable appliances such as information processors (e.g., microprocessors), AV devices, game machines and the like.
2. Description of Related Art
With widespread use of electronic devices for operating portable appliances such as portable telephones, personal digital assistants (PDA), portable information terminals, AV devices and others on batteries, it is becoming more important to decrease both power consumption during operation and power consumption during standby.
High-speed operation at low voltage is enabled by setting a low threshold voltage for MOS transistors. Since the power consumption is proportional to the square of operating voltage, the power consumption during operation can also be reduced.
On the other hand, the power consumption during standby increases where the threshold voltage is set low, because sub-threshold current flows.
In order to solve the above-mentioned problems, Japanese Unexamined Patent Publication No. HEI 3(1991)-082151 proposes a method for decreasing standby current. In this method, the threshold voltage of a MOS transistor is set low for high-speed operation and only during standby, a reverse bias is applied between a source and a substrate (or a well) to raise the threshold voltage of the MOS transistor.
For such application of the reverse bias between the source and the substrate (or the well), there are a method of generating a well potential or a substrate potential within a chip using a well or substrate bias generating circuit and a three power sources method in which two additional power sources are provided for applying two well biases.
Also Japanese Unexamined Patent Publication No. HEI 9(1997)-214321 proposes a method for suppressing a leakage current to a minimum by dynamically controlling the threshold voltage of one type or both types of transistors of a CMOS inverter.
As an example of the aforesaid well or substrate bias generating circuit, a charge pump circuit is mentioned as disclosed in IEEE Journal of Solid-State Circuits, Vol.34, No. 11 Nove. 1999, pp. 1492-1500.
However, in order to operate this charge pump circuit, a power source of about 11 xcexcA and an area of about 0.14 mm2 are required. Taking the power consumption of the charge pump circuit into consideration, the reduction of the power consumption during standby is limited. As described below, the standby current of a microprocessor with about 4,000,000 elements is about 14 xcexcA at room temperature. If the threshold voltage of a MOS transistor is raised 0.2 V by applying a reverse bias of 1 V between the source and the well by the charge pump circuit, the standby current decreases by about two digits and becomes smaller than 1 xcexcA. Thus, the standby current is almost determined by the power consumption of the charge pump circuit. Furthermore, generally, regarding this charge pump circuit, a triple well structure is required for stabilization of operation. This results in a complicated production process and consequently an increase in the cost of production.
In the three power sources method in which two well biases are applied, exclusive-use power sources are added for decreasing the power consumption during standby. That is out of size-, weight- and cost-reduction of battery-operated portable appliances. Also, in this method, the three well structure is required for three power sources.
In order to control the threshold voltage of either one type or both types of transistors of the CMOS inverter, a well or substrate bias generating circuit is also required for applying a bias to control the threshold voltage, in addition to a power source for the CMOS inverter. That gives rise to the same problems as described above. Further, no disclosure is found about adjustment of the threshold voltage of both the types of transistors before the threshold voltage is changed by the application of the bias. If both the types of transistors have equal leakage currents before the bias is applied to the well or substrate of the CMOS inverter, the standby power consumption is not decreased sufficiently by applying the well or substrate bias only to one type of transistors to raise the threshold voltage.
The present invention has been made in the light of the above-described problems, and an object of the invention is to provide an integrated CMOS semiconductor circuit whose power consumption during standby is decreased without increasing the number of exclusive-use power sources, additionally providing a substrate bias generating circuit which would increase the power consumption and the area of a chip or forming the triple well structure which would make the production process complicated for reducing the power consumption during standby.
The present invention provides an integrated CMOS semiconductor circuit comprising: an internal circuit composed of CMOS transistors including P- and N-channel transistors each having a gate electrode and source/drain regions formed on a semiconductor substrate, the internal circuit functioning in at least two states including an active state in which data is input and output, and a standby state in which a state of the internal circuit is maintained; an external circuit composed of any electrical element and provided with a power source; and a switch portion which is enable to apply, in the standby state in the internal circuit, a reverse bias between the source region and the substrate of either one of the P- and N-channel transistors of the internal circuit by the power source of the external circuit.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.